ame, inc. rev.a.01 1 at209s pci arbiter and clock buffer l pci arbiter extend pci devices from one to three l pci clock frequency support pci clock range from 25mhz to 66mhz l zero delay buffer generate four zero delay clock sources support frequency range from 25mhz to 66mhz the at209s is an integrated device that contains a pci arbiter and a clock buffer. pci arbiter extends system pci devices without piecing other circuit to simplify de- sign complexity and increase systems stability. pci arbiter also provides stop# input pin with that extended pci devices instruct the master to prematurely end the transaction on the current data phase same as one in pci specification. clock buffer is a high performance and low jitter zero delay buffer that provides synchronization between the input and output. the synchronization is established via clko feed back to the input of a build-in pll. pciclki is the clock input of the clock buffer. in the absence of pciclki input, will be in the power down mode. in this mode, the pll is turned off and the output buffers are pulled low. power down mode provides the lowest power consumption for a standby condition. n general description n features l all ame' s lead free products meet rohs standards
ame, inc. 2 rev.a.01 pci arbiter and clock buffer at209s n pin configuration nc 1 28 avcc pcistop# 2 27 pciclki sysreq# 3 26 pcirst# sysgnt# 4 25 avss pcireq1# 5 24 vss vss 6 23 pciclkout pcignt1# 7 22 pciclk1 pcireq2# 8 21 vcc vcc 9 20 pciclk2 pcignt2# 10 19 pciclk3 pcireq3# 11 18 pciclk4 pcignt3# 12 17 vss nc 13 16 nc nc 14 15 nc a t 2 0 9 s ? ordering information at 209s - commercial standard AT209SG - green device with commercial standard
ame, inc. rev.a.01 3 at209s pci arbiter and clock buffer n pin description i/o type function in input pin out output pin pwr power pin pin no. pin name i/o type function 26 pcirst# in pci bus reset# 2 pcistop# in pci bus stop# (internal 47k pull-up resistor) 3 sysreq# out request signal to chipset 4 sysgnt# in grant signal from chipset (internal 47k pull-up resistor) 5 pcireq1# in request signal from pci bus (internal 47k pull-up resistor) 7 pcignt1# out grant signal to pci bus 8 pcireq2# in request signal from pci bus (internal 47k pull-up resistor) 10 pcignt2# out grant signal to pci bus 11 pcireq3# in request signal from pci bus (internal 47k pull-up resistor) 12 pcignt3# out grant signal to pci bus table 1. pci arbiter fsm group signal, power; vcc3v (3.3v)
ame, inc. 4 rev.a.01 pci arbiter and clock buffer at209s pin no. pin name i/o type function 18 pciclk4 out pciclk output 19 pciclk3 out pciclk output 20 pciclk2 out pciclk output 22 pciclk1 out pciclk output 23 pciclkout out pll feedback and internal feedback on this pin 27 pciclki in pclclk input reference frequency n pin description table 2. clock buffer group signal ---- power: vcc23 (2.5v or 3.3v) pin no. pin name i/o type function 6 vss pwr ground 9 vcc pwr 3.3v power 17 vss pwr ground 21 vcc pwr 3.3v power 24 vss pwr ground 25 avss pwr ground for pll 28 avcc pwr 3.3v power for pll table 3. power signal
ame, inc. rev.a.01 5 at209s pci arbiter and clock buffer symbol parameter test conditions min typical max unit vil input low voltage 0.8 v vih input high voltage 2 v vol output low voltage ioi=30ma; vcc3v=3.3v 0.4 v voh output high voltage ioh=30ma; vcc3v=3.3v 2.4 v measure between 0.8v and 2v, cl=30p measure between 0.8v and 2v, cl=30p measure at 0.5*vin & vout, cl=30p pciclki buffer input frequency 25m 50m hz propagation delay time 250 tr output rise time ns tf output fall time ns 2 tpd ns duty1 output duty cycle (0.5*vcc as a reference) input duty cycle=50% 45 55 % 2 symbol parameter test conditions min typical max unit vcc power pin 3.15 3.3 3.45 v vss ground pin 0 v avcc power pin for pll 3.15 3.3 3.45 v avss ground pin for pll 0 v n quick reference data gnd = 0v; vcc = 3.3v; 0 o c < temp < 85 o c table 4. power/ground pin table 5. clock buffer block
ame, inc. 6 rev.a.01 pci arbiter and clock buffer at209s symbol parameter test conditions min typical max unit vil input low voltage 0.8 v vih input high voltage 2.0 v vol output low voltage 0.4 v voh output high voltage 2.4 ns tdcko ns output delay from pciclk rising edge to output valid 8 10 n quick reference data table 6. pci arbiter fsm
ame, inc. rev.a.01 7 at209s pci arbiter and clock buffer pll pciclk out pciclk1 pciclk2 pciclk3 pciclk4 pciclki figure 2. clock buffer block diagram output-to-output skew since the pciclkout and the pciclk(1-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. if all outputs are equally loaded, zero phase difference will maintained from pciclki to all outputs. if applications requiring zero output-output skew, all the outputs must equally loaded. if the pciclk(1-4) outputs are less loaded than pciclkout, pciclk(1-4) outputs will lead it; and if the pciclk(1-4) is more loaded than pciclkout, pciclk(1-4) will lag the pciclkout.
ame, inc. 8 rev.a.01 pci arbiter and clock buffer at209s pciclki input and all outputs loaded equally pciclki pciclkout pciclk(1-4) zero delay pciclki pciclkout pciclk(1-4) delayed pciclki pciclkout pciclk(1-4) advanced pciclki input and pciclk(1-4) outputs loaded equally, with pciclkout loaded more. pciclki input and pciclk(1-4) outputs loaded equally, with pciclkout loaded less . figure 3. timing diagrams with different loading configurations
ame, inc. rev.a.01 9 at209s pci arbiter and clock buffer n package dimension ssop-28 b e e 1 e 14 15 top view 1 28 d a 1 a 2 seating plane 0.004 max front view a min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 - 1.50 - 0.059 b 0.20 0.30 0.008 0.012 d 9.80 10.00 0.386 0.394 e1 3.81 4.00 0.150 0.157 e e 5.80 6.20 0.228 0.244 h l 0.41 1.27 0.016 0.500 q 0 o 8 o 0 o 8 o symbols millimeters inches 0.635basic 0.025basic 0.380basic 0.015basic h side view a" l detal : a" 0' seating plane gauge plane
life support policy: these products of ame, inc. are not authorized for use as critical components in life-support devices or systems, without the express written approval of the president of ame, inc. ame, inc. reserves the right to make changes in the circuitry and specifications of its devices and advises its customers to obtain the latest version of relevant information. ? ame, inc. , auguest 2007 document: att-ds209s-a.01 corporate headquarter u.s.a. (subsidiary) ame, inc. analog microelectronics, inc. 2f, 302 rui-guang road, nei-hu district 3100 de la cruz blvd., suite 201 taipei 114, taiwan. santa clara, ca. 95054-2046 tel : 886 2 2627-8687 tel: (408) 988-2388 fax: 886 2 2659-2989 fax: (408) 988-2489 www.ame.com.tw e-mail: sales@ame.com.tw
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